BASIC_MCP

Multicycle path - Basic understanding.

Best Synthesis Approach - in Market

In this post, I am very interested to share the best practised synthesis approach in Market.

I expect my fellow friends to share and comment to make it more fruitful. :)

Methodology:

1) To start with normal initial mapping followed by initial optimization, followed by clock gating insertion ( few companies follow it as a standard by performing clk gate insertion at early stage)
[Quiz -  what happens if clock gate is inserted before your final top optimization]

2) I like to make few things clear here; when we see the syntax of optimization (say compile or synthesize), we do have a option of map_effort (low/medium/high) option, please try to understand the importance of why we have this option, I shall cover in the last page of this Discussion. (AXN1* - AXN alias for action)

3) Multibit - optimization - (will write more with a example)

4) DFT insertion - scan stitching - check coverage:

5) Final top optimization - I will add, what are all the options that we perform during final optimization.
[to cover up -reports to analyzed and checked]


[Courtesy Cadence - @]
http://www.cadence.com/Community/CSSharedFiles/blogs/ii/2012/Richard_Goering/Synthesis.jpg

Date - 28/9/2013

The reiteration process and strategy discussion will be updated soon.

Hariharan GB

Multi Cycle path - Completely Explained

Here I would like to start from the basics of the multicycle path, and like to include slow to fast (fast to slow) clock relation.
Please feel free to comment and add valuable points if you have.

Basic Understanding:
- Hope the audience will be already aware of Single (launch and capture clock) MCP.
- Hope you also familiar with, the start and end attribute in the set_multicycle_path command does.
- Hope you are familiar with, the setup and hold option that we mention in the command.

Note - If you are not sure about the above concepts, please scroll check Basic_MCP at my blog to get the basics of MCP first clear.

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Clock domain crossing

What is this clock domain crossing actually means? 

Why people show up as a big concern in constraining?

Is it a Big Fish to deal or a Normal Fish to cook.... 

... The very famous Document that everyone will have for CDC

Doc1 - http://www.sunburst-design.com/papers/CummingsSNUG2008Boston_CDC.pdf

Just follow up this site (Doc 2)- and you shall be able to get why we need a handshake methodology, for CDC.

Doc 2 - https://filebox.ece.vt.edu/~athanas/4514/ledadoc/html/pol_cdc.html

Ok, Let us start with the basic understanding from here.

When we say 2 clocks crossing; think in all possible assumptions like:

- Both the clocks may be of different/same source; they might differ in frequencies (slighter/larger).

- One thing to worry about is how we can get the data without missing?

Can we check a CDC timing check in Static Timing Analysis?

Assume that we have 2 clocks for launch and capture:

3 Major issues as we already know in CDC. 

1) Metastability            2) Data incoherence        3) Data Loss 

We use synchronizers, as given in the Doc 1 and 2, we have our problem resolved from RTL perspective.

Here we will see, how a timing report looks like?

...... to be continued.... 

Hariharan GB

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