Thursday, September 26, 2013

Best Synthesis Approach - in Market

In this post, I am very interested to share the best practised synthesis approach in Market.

I expect my fellow friends to share and comment to make it more fruitful. :)

Methodology:

1) To start with normal initial mapping followed by initial optimization, followed by clock gating insertion ( few companies follow it as a standard by performing clk gate insertion at early stage)
[Quiz -  what happens if clock gate is inserted before your final top optimization]

2) I like to make few things clear here; when we see the syntax of optimization (say compile or synthesize), we do have a option of map_effort (low/medium/high) option, please try to understand the importance of why we have this option, I shall cover in the last page of this Discussion. (AXN1* - AXN alias for action)

3) Multibit - optimization - (will write more with a example)

4) DFT insertion - scan stitching - check coverage:

5) Final top optimization - I will add, what are all the options that we perform during final optimization.
[to cover up -reports to analyzed and checked]


[Courtesy Cadence - @]
http://www.cadence.com/Community/CSSharedFiles/blogs/ii/2012/Richard_Goering/Synthesis.jpg

Date - 28/9/2013

The reiteration process and strategy discussion will be updated soon.
Hariharan GB

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